| Per Bjesse | ||
| Publications | ||
| Word Level Bitwidth Reduction for
Unbounded Hardware Model Checking Per Bjesse In Formal Methods in System Design, 2009. [link] | ||
| Word Level Sequential Memory Abstraction
for Model Checking Per Bjesse In International Conference on Formal Methods in Computer Aided Design, 2008. [download PDF] | ||
| A Practical Approach to Word Level Model
Checking of Industrial Netlists Per Bjesse In International Conference on Computer Aided Verification, 2008. [download PDF] | ||
| A Compositional Approach to the Combination of Combinational and
Sequential Equivalence Checking of Circuits Without Known Reset States In-Ho Moon, Per Bjesse, Carl Pixley In Design Automation and Test in Europe, 2007. [download PDF] | ||
| Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces In-Ho Moon, Per Bjesse, Carl Pixley In IEEE International High Level Design Validation and Test Workshop, 2006. [download PDF] | ||
| Automatic Generalized Phase Abstraction for Formal Verification Per Bjesse, James Kukula In International Conference on Computer Aided Design, 2005. [download PDF] | ||
| DAG-Aware Circuit Compression For Formal Verification Per Bjesse, Arne Boralv In International Conference on Computer Aided Design, 2004. [download PDF] | ||
| Using Counter Example Guided Abstraction Refinement to Find Complex Bugs Per Bjesse, James Kukula In Design Automation and Test in Europe, 2004. [download PDF] | ||
| Guiding SAT Diagnosis with Tree Decompositions Per Bjesse, James Kukula, Robert Damiano, Ted Stanion, Yunshan Zhu In Proceedings of International Symposium on the Theory and Applications of Satisfiability Testing, 2003. [download PDF] | ||
| Design Automation with Mixtures of Proof Strategies for Propositional Logic Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna In Transactions on Computer Aided Design, August 2003. | ||
| A Proof Engine Approach to Solving Combinational Design Automation Problems Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna In Design Automation Conference, 2002. [download PDF] | ||
| Gate Level Description of Synchronous Hardware and Automatic Verification Based on Theorem Proving PhD thesis, Chalmers Technical University, 2001. [download PDF] | ||
| Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers Per Bjesse, Tim Leonard, Abdel Mokkedem In International Conference on Computer Aided Verification, 2001. [download PDF] | ||
| SAT-based Verification without State Space Traversal Per Bjesse, Koen Claessen In International Conference on Formal Methods in Computer Aided Design, 2000. [download PDF] | ||
| Symbolic Reachability Analysis based on SAT-Solvers Parosh Abdulla, Per Bjesse, Niklas Een In Tools and Algorithms for the Construction and Analysis of Systems, 2000. [download PDF] (best paper award) | ||
| Symbolic Model Checking with Sets of States Represented as Formulas Per Bjesse Technical report CS-1999-102, Department of Computer Science, Chalmers Technical University, 1999. [download PDF] | ||
| Automatic Verification of Combinational and Pipelined FFT Circuits Per Bjesse In International Conference on Computer Aided Verification, 1999. [download PDF] | ||
| Lava: Hardware design in Haskell Per Bjesse, Koen Claessen, Mary Sheeran Satnam Singh. In International Conference on Functional Programming, 1998. [download PDF] | ||
| Specification of signal processing programs in a pure functional language and compilation to distributed architectures MSc Thesis in Electrical Engineering, Chalmers Technical University, June 1997. [download PDF] | ||
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